Germanium on insulator fabrication via epitaxial germanium bonding

ABSTRACT

A method of forming a germanium-on-insulator (GOI). An epitaxial germanium layer is formed on top of a first substrate. A first dielectric film is formed on top of the epitaxial germanium layer. A second substrate is provided. The first substrate is bonded to the second substrate by bonding the first dielectric film to the second substrate. The bonding resulted in a bonded wafer pair. The first substrate is removed after the bonding to expose epitaxial germanium layer to form the GOI substrate.

BACKGROUND

1. Field

This disclosure pertains to a method of fabricating agermanium-on-insulator (GOI) substrate and a method of bonding anepitaxial germanium layer to a semiconductor substrate to form a GOIsubstrate.

2. Discussion of Related Art

There is an increasing interest in using silicon-germanium (Si—Ge) alloyas a material for microelectronic and optoelectronic deviceapplications. Germanium (Ge) is known to have high carrier mobility(e.g., high hole and electron mobility) and optical absorption ascompared to silicon (Si). This is one reason why Ge is useful fordevices that require enhanced performance and/or high quantumefficiency. Embodiments of devices that would benefit from the use of aGe film include metal-oxide-semiconductor (MOS) transistors, opticaldetectors, and other optoelectronic devices, to name a few. There isalso an increasing interest in bonding a germanium layer onto aninsulator that is formed on a semiconductor substrate to form the GOIbecause the insulator layer in the semiconductor substrate helpsreducing current leakage in the semiconductor device that is formed inthe germanium layer.

There are generally two methods for forming a GOI substrate. In thefirst method, a crystalline Ge donor wafer is transferred (or bonded)onto a semiconductor wafer handle having an insulation layer. Ionexfoliation is then used to remove portions of the Ge donor wafer toleave a Ge layer bonded to the semiconductor wafer. Using a crystallineGe donor wafer to transfer Ge onto a wafer handle is costly. Forinstance, the crystalline Ge donor must be polished to the desiredthickness which is time consuming and expensive. It is thus difficultand costly to remove surface non-uniformity after the ion exfoliation.

In the second method, an epitaxial Ge layer is formed on top of asemiconductor wafer handle having an insulation layer. Currently, anepitaxial Ge layer cannot be directly bonded to a wafer handle due tothe high roughness inherent in the Ge layer. Direct wafer bondingrequires smooth surfaces of about <0.5 nm to <1.5 nm RMS roughness. Anepitaxial germanium (Ge) layer usually has a roughness of about >2 nm RMto >4 nm RMS. Such roughness in an epitaxial Ge layer makes directbonding of the Ge layer to an insulator on a semiconductor substrate (orwafer handle) difficult. In addition, to treat the surface of theepitaxial Ge so as to provide it with a smooth surface is difficult andexpensive. For example, chemical mechanical polishing of an epitaxial Gelayer surface is time consuming.

There is thus a need for a new method of forming a GOI substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure is illustrated by way of embodiment and not by way oflimitation in the figures of the accompanying drawings in which likereferences indicate similar elements. The invention may best beunderstood by referring to the following description and accompanyingdrawings that are used to illustrate embodiments of the invention. Inthe drawings:

FIGS. 1A-1E illustrate an exemplary GOI substrate at various stages offabrication;

FIGS. 2A-2F illustrate another exemplary GOI substrate at various stagesof fabrication;

FIGS. 3A-3F illustrate another exemplary GOI substrate at various stagesof fabrication;

FIG. 4 illustrates an exemplary method of bonding an epitaxial Ge layerto a semiconductor substrate wafer in accordance to the embodiments ofthe present invention;

FIG. 5 illustrates another exemplary method of bonding an epitaxial Gelayer to a semiconductor substrate wafer in accordance to theembodiments of the present invention;

FIG. 6 illustrates yet another exemplary method of bonding an epitaxialGe layer to a semiconductor substrate wafer in accordance to theembodiments of the present invention.

FIG. 7 illustrates a GOI substrate formed in accordance to someembodiments of the present invention;

FIG. 8 illustrates an exemplary semiconductor device (e.g., atransistor) that can he fabricated in a GOI substrate formed inaccordance to some of the embodiments of the present invention; and

FIG. 9 illustrates another exemplary semiconductor device (e.g., adetector) that can be fabricated in a GOI substrate formed in accordanceto some of the embodiments of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Exemplary embodiments are described with reference to specificconfigurations and techniques. Those of ordinary skill in the art willappreciate the various changes and modifications to be made whileremaining within the scope of the appended claims. Additionally, wellknown elements, devices, components, circuits, process steps and thelike are not set forth in detail.

The embodiments of the present invention direct to methods of forming agermanium-on-insulator (GOI) substrate. Throughout the disclosure, theterm “bonded wafer pair” refers to a first semiconductor substratehaving an epitaxial germanium layer formed thereon being bonded to asecond semiconductor substrate. The first semiconductor substrate isbonded to a second semiconductor substrate through at least onedielectric layer. The term “semiconductor substrate” used in thisdisclosure includes a Si substrate, a Si-containing substrate, a Sisubstrate having an oxide layer (e.g., silicon dioxide), or asilicon-on-insulator (SOI) substrate. The silicon substrate may bemonocrystalline, polycrystalline, or bulk silicon. The term“semiconductor substrate” may also include other material typically usedto fabricate semiconductor devices such as gallium arsenide.

It is difficult to form a crystalline germanium layer on a dielectriclayer. A dielectric layer is typically amorphous and as such, it isdifficult for a crystalline germanium layer to form thereon. Even if agermanium layer can be formed on a dielectric layer, it will beamorphous and lacking any crystalline structure. It is also difficult tobond an epitaxial germanium film onto a dielectric layer due to theinherent roughness of the epitaxial germanium film. The embodimentsdisclose methods of forming a GOI substrate that does not requirebonding a germanium film onto a semiconductor substrate and does notrequired growing a germanium film on a dielectric layer. The embodimentsdisclose methods of forming a GOI substrate that includes forming adielectric layer on an epitaxial germanium and then bonding thatdielectric layer onto another surface to form the GOI substrate.

In one embodiment, an epitaxial Ge layer is formed on a firstsemiconductor substrate (e.g., Si substrate). The epitaxial Ge layer hasa rough surface generally about 2 nm or greater than 2 nm RMS roughness.A first dielectric layer (e.g., silicon dioxide (SiO₂) or siliconnitride (Si₃N₄)) is formed over the epitaxial Ge layer, over the roughsurface. The first dielectric layer conforms to the roughness pattern inthe epitaxial Ge layer. The first dielectric layer is sufficiently thickto cover the roughness in the epitaxial Ge layer. A second semiconductorsubstrate (e.g., Si substrate) is provided. The first and the secondsemiconductor substrates are bonded together in a way that the firstdielectric layer formed over the epitaxial Ge layer is bonded to a cleansurface of the second semiconductor substrate. After the bonding, thefirst semiconductor substrate is removed and the structure remained is aGOI substrate. The GOI substrate includes the second semiconductorsubstrate, the dielectric layer, and the epitaxial Ge layer.

In an alternative embodiment, the second semiconductor substrateincludes a second dielectric layer. When the first semiconductorsubstrate and the second semiconductor substrate are bonded together,the first dielectric layer and the second dielectric layer are directlybonded to each other. After the bonding, the first semiconductorsubstrate is removed and the structure remained is a GOI substrate. TheGOI substrate includes the second semiconductor substrate, the first andsecond dielectric layers, and the epitaxial Ge layer.

FIGS. 1A-1E illustrate various stages of forming a GOI substrate 100 inaccordance to some embodiments of the present invention. In FIG. 1A, afirst semiconductor substrate 102 is provided. The first semiconductorsubstrate 102 can be any suitable material that an epitaxial Ge layercan be formed thereon and be removed from. The semiconductor substrate102 is typically a Si wafer. It is to be appreciated that the Si wafermay be replaced by other suitable semiconductor substrate such as Ge andgallium arsenide.

In FIG. 1B, an epitaxial Ge layer 104 is formed on top of the firstsemiconductor substrate 102. In one embodiment, the epitaxial Ge layer104 has a surface with a roughness approximately greater than 2 nm RMS.In another embodiment, the epitaxial Ge layer 104 has a surface with aroughness approximately greater than 4 nm RMS. The epitaxial Ge layer104 has a thickness 101 that may be less than 3000 Å. In someembodiment, the epitaxial Ge layer 104 has a thickness 101 ranging fromabout 100-4000 Å. The epitaxial Ge layer 104 can be formed usingconventional methods such as chemical vapor deposition (CVD) or plasmaenhanced CVP as is known in the art. In one embodiment, a germanium gassource (e.g., germane) is floated over the substrate 102, which createsa gas phase reaction with the surface of the first semiconductorsubstrate 102. The epitaxial Ge layer 104 is formed on the surface ofthe first semiconductor substrate 102 as a result of the gas phasereaction.

In FIG. 1C, a dielectric layer 106 is formed over the epitaxial Ge layer104. As shown in FIG. 1B, the surface of the epitaxial Ge layer 104 isrough and thus difficult for a direct wafer bonding to the epitaxial Gelayer 104. Forming the dielectric layer 106 over the epitaxial Ge layer104 covers the rough surface on the epitaxial Ge layer 104 and allowsbonding to the dielectric layer 106. In this way, the epitaxial Ge layer104 can be bonded to another wafer through the dielectric layer 106.

The dielectric layer 106 is typically an oxide film such as silicondioxide (SiO₂), silicon nitride (Si₃N₄), hafnium oxide (HfO₂), strontiumtintanate (SrTiO₃), tantalum penta oxide (Ta₂O₅), titanium oxide (TiO₂),zirconium oxide (ZrO₂), aluminum oxide (Al₂O₃), and yttrium oxide(Y₂O₃), etc. The dielectric layer 106 can be a high-k dielectric layeror a low-k dielectric layer. It is more preferable to have a high-kdielectric layer 106 for a thinner and more efficient insulation layer.The dielectric layer 106 is compatible to a semiconductor substrate,which it will be bonded to, e.g., a silicon substrate. The dielectriclayer 106 is formed by a conventional method such as CVD or plasmaenhanced CVD.

In one embodiment, the dielectric layer 106 is sufficiently thick tocover the roughness on the surface of the epitaxial Ge layer 104. In oneembodiment, the dielectric layer 106 has a thickness 103 greater than3000 Å. In another embodiment, the dielectric layer 106 has a thickness103 greater than 6000 Å. Portions of the dielectric layer 106 may beremoved (e.g., by polishing or etching) to provide the dielectric layer106 with a smaller thickness (e.g., a thickness 107 as shown in FIG. 1Fthat is smaller than the thickness 103) if desired. In one embodiment,the thickness 103 is about 3000 Å and the thickness 107 is about500-2000 Å. In one embodiment, the dielectric layer 106 is polishedusing a conventional method such as chemical mechanical polishing (CMP)to remove some of the dielectric layer 106.

In FIG. 1D, a second semiconductor substrate 110 is provided. The secondsemiconductor substrate 110 can be any suitable substrate typically usedfor fabricating an electronic device therein. The second semiconductorsubstrate 110 can be a Si wafer.

In FIG. 1E, the first semiconductor substrate 102 and the secondsemiconductor substrate 110 are bonded together. In particular, thefirst dielectric layer 106 is bonded to a surface of the secondsemiconductor substrate 110. After the bonding, the first dielectriclayer 106 is buried between the second semiconductor substrate 110 andthe epitaxial Ge layer 104.

A conventional bonding chamber can be used to bond the firstsemiconductor substrate 102 and the second semiconductor substrate 110together. One embodiment of such conventional wafer-bonding chamber isthe EVG 850 Series or the EVG 650 Series wafer bonders made by EV Group,Austria. An appropriate bonding condition for a wafer-bonding chamber isfirst obtained. The wafer-bonding chamber must be able to maintain thebonding temperature and bonding pressure. In one embodiment, the bondingtemperature is obtained by heating up the wafer-bonding chamber to adesired bonding temperature, (e.g., a temperature ranging from 22° C. to600° C.). In one embodiment, the bonding temperature is roomtemperature. In another embodiment, a chuck, which is used to hold thewafers, is heated up to the desired bonding temperature. The bondingpressure is obtained by evacuating the wafer-bonding chamber to a vacuumcondition. The pressure of the wafer-bonding chamber can be obtained byusing a conventional mechanical pump connected to the wafer-bondingchamber. The pressure of the wafer-bonding chamber is a pressure underwhich the mutual sticking of the Ge wafer to the Si wafer does notcommence and that the Ge wafer and the Si wafer are held with respect toeach other. In one embodiment, the pressure of the wafer-bonding chamberis below 1 Torr. In another embodiment, the pressure of thewafer-bonding chamber is about 1 mili Torr. In another embodiment, thepressure is atmospheric pressure.

The wafer-bonding chamber provides a clean and dry environment for thebonding to occur. In addition, prior bonding, the surface of the firstdielectric layer 106 and the surface of the surface of the secondsemiconductor substrate 110 that is to be bonded to the first dielectriclayer 106 are cleaned so that they have clean, substantially particlefree, and atomically smooth surfaces to facilitate a good bonding. Thepresent of small particles (e.g., particles having size larger thanabout 0.1-0.2 μm) would interrupt the bonding of the wafers and lead tovoid and decreasing bonding strength.

In one embodiment, a moisture containing carrier gas such as nitrogen,xenon and helium is introduced into the wafer-bonding chamber at a flowrate of about 10 ml-100 ml per minute to facilitate the bonding.

The bonding may occur with either the second semiconductor substrate 110or the first semiconductor substrate 102 being on the bottom or being ontop. In one embodiment, the second semiconductor substrate 110 is placedon the chuck in the bonding chamber and the first semiconductorsubstrate 102 is place on the top of the second semiconductor substrate110 with the first dielectric layer 104 facing the second semiconductorsubstrate 110 for bonding.

A local force is applied either to the to the first semiconductorsubstrate 102 or the second semiconductor substrate 110 to initiate thebonding. In one embodiment, the local force is a force applied to onepoint either on the first semiconductor substrate 102 or the secondsemiconductor substrate 110. In another embodiment, the local force isapplied to a region near an edge of either the first semiconductorsubstrate 102 or the second semiconductor substrate 110 using a Teflonpin conveying a force ranging from 3 Newton to 4000 Newton pressing downon that region. In a preferred embodiment, the local force is about 2000Newton. Once the bonding is initiated, the bonding is propagated tocompletely bond the first dielectric layer 104 to the secondsemiconductor substrate 110. In one embodiment, the bonding is allowedto continue for an amount of time (e.g., 30 seconds or more) sufficientto completely bond the first dielectric layer 104 to the secondsemiconductor substrate 110 to form a bonded wafer pair.

After the bonding, the first semiconductor substrate 102 is removedusing methods such as etching, grinding, and/or ion exfoliation. Ionexfoliation generally refers to a process that uses ion implantation toimplant ions into a substrate such as the first semiconductor substrate102, to a predetermined depth. The ions implanted form a cleaving planeat the predetermined depth within the substrate. The substrate can thenbe cleaved at the cleaving plane and be removed. After the firstsemiconductor substrate 102 is removed, the remaining structure formsthe GOI substrate 100.

In one embodiment, prior to the removal of the first semiconductorsubstrate 102, the bonded wafer pair is annealed to strengthen thebonding interface and the bonding of the bonded wafer pair. Theannealing process removes and diffuses any moisture trapped at theinterface of the first dielectric layer 106 and the second semiconductorsubstrate 110. In one embodiment, the annealing process takes place inthe same wafer-bonding chamber that is used for the bonding. Theannealing process occurs at a temperature that is sufficient tostrengthen the bonded wafer pair without causing damages to the bondedwafer pair. There are several ways for annealing the bonded wafer pair.In one embodiment, the bonded wafer pair is annealed at a temperaturegreater that 100° C. The annealing temperature can be as high as 600° C.or as high as 75% of the melting temperature of the wafers. In anotherembodiment, the bonded wafer pair is annealed in the presence of acarrier gas such as nitrogen and at a temperature of about 150° C. Inone embodiment, the annealing temperature (e.g., 100-150° C.) isobtained with the temperature being ramped up to the annealingtemperature at a rate of 1° C./minute while the bonded wafer pairresides in the chamber. After the annealing temperature is obtained, thebonded wafer pair is held in the chamber for a predetermined amount oftime sufficient to anneal the bonded wafer pair, e.g., 1-20 hours. It ismore advantageous to anneal the bonded wafer pair at a lower temperatureand longer duration to prevent damages to the bonded wafer pair. Thebonded wafer pair is then allowed to cool down with the temperatureramping down at a rate of approximately 1° C./minute to 2° C./minute. Itis to be appreciated that the bonded wafer pair may be annealed usingconventional annealing methods and that the annealing conditions recitedabove is only an exemplary condition and not a limitation.

In the embodiments where the bonded wafer pair is annealed, the firstsemiconductor substrate 102 is removed after the annealing to yield theGOI substrate 100. In the embodiments shown in FIGS. 1A-1E, the firstsemiconductor substrate 102 can be removed by grinding back (e.g., usingCMP) to expose the epitaxial Ge layer 104. Alternatively, the firstsemiconductor substrate 102 can be removed by an etching process toexpose the epitaxial Ge layer 104. Alternatively yet, the firstsemiconductor substrate 102 can be removed by a combination of a grindback and an etching processes. After the first semiconductor substrate102 is removed, the GOI is formed having the epitaxial Ge layer 104 andthe dielectric layer 106 bonded to the second semiconductor substrate110.

In one embodiment, the first semiconductor substrate 102 is partiallyremoved by a grind back process. The first semiconductor substrate 102can then be polished using a CMP process to remove the majority of thefirst semiconductor substrate 102 from the bonded wafer pair. The firstsemiconductor substrate 102 can also be etched away using a chemistrythat is selective to remove the substrate 102 to complete the removalprocess of the substrate 102.

FIGS. 2A-2F illustrate various stages of forming a GOI substrate 200 inaccordance to some embodiments of the present invention. The GOIsubstrate 200 is similar to the GOI substrate 100 except that the secondsemiconductor substrate includes an additional dielectric layer.

In FIG. 2A, a first semiconductor substrate 202 is provided. The firstsemiconductor substrate 202 can be any suitable material that anepitaxial Ge layer can be formed thereon and be removed from. Thesemiconductor substrate 202 is typically a Si wafer.

In FIG. 2B, an epitaxial Ge layer 204 is formed on top of the firstsemiconductor substrate 202. In one embodiment, the epitaxial Ge layer204 has a surface with a roughness approximately greater than 2 nm RMS.In another embodiment, the epitaxial Ge layer 204 has a surface with aroughness approximately greater than 4 nm RMS. The epitaxial Ge layer204 has a thickness 201 that may be less than 3000 Å. In someembodiment, the epitaxial Ge layer 204 has a thickness 201 ranging fromabout 100-4000 Å. The epitaxial Ge layer 204 can be formed usingconventional methods such as chemical vapor deposition (CVD) or plasmaenhanced CVP as is known in the art.

In FIG. 2C, a first dielectric layer 206 is formed over the epitaxial Gelayer 204. As shown in FIG. 2B, the surface of the epitaxial Ge layer204 is rough and thus difficult for a direct wafer bonding to theepitaxial Ge layer 204. Forming the first dielectric layer 206 over theepitaxial Ge layer 204 covers the rough surface on the epitaxial Gelayer 204 and allows bonding to the first dielectric layer 206. In thisway, the epitaxial Ge layer 204 can be bonded to another wafer throughthe first dielectric layer 206. The first dielectric layer 206 issimilar to the dielectric layer 106 previously described and can be anoxide film such as SiO₂, Si₃N₄, HfO₂, SrTiO₃, Ta₂O₅, TiO₂, ZrO₂, Al₂O₃,and Y₂O₃, etc. The first dielectric layer 206 is formed by aconventional method such as CVD or plasma enhanced CVD.

In one embodiment, the first dielectric layer 206 is sufficiently thickto cover the roughness on the surface of the epitaxial Ge layer 204. Inone embodiment, the first dielectric layer 206 has a thickness 203greater than 3000 Å. In another embodiment, the first dielectric layer206 has a thickness 203 greater than 6000 Å. Portions of the firstdielectric layer 206 may be removed (e.g., by polishing or etching) toprovide the first dielectric layer 206 with a smaller thickness (e.g., athickness 207 as shown in FIG. 2F that is smaller than the thickness203) if desired. In one embodiment, the thickness 203 is about 3000 Åand the thickness 207 is about 500-2000 Å. In one embodiment, the firstdielectric layer 206 is polished using a conventional method such aschemical mechanical polishing (CMP) to remove some of the firstdielectric layer 206.

In FIG. 2D, a second semiconductor substrate 210 is provided. The secondsemiconductor substrate 210 can be any suitable substrate typically usedfor fabricating an electronic device therein. The second semiconductorsubstrate 210 can be a Si wafer.

In FIG. 2E, a second dielectric layer 212 is formed on top of the secondsemiconductor substrate 210. The second dielectric layer 212 is similarto the first dielectric layer 206 and can be formed of similar materialand using similar methods as those used for the first dielectric layer206. The second dielectric layer 212 has a predetermined thickness 205.The second dielectric layer 212 and the first dielectric layer 206should have a combined thickness 209 that is sufficient to insulate thedevice that will be formed on the GOI substrate 200. In one embodiment,the combined thickness 209 is between 500-3500 Å.

In FIG. 2F, the first semiconductor substrate 202 and the secondsemiconductor substrate 210 are bonded together. In particular, thefirst dielectric layer 206 is bonded to the second dielectric layer 212.After the first bonding, the first dielectric layer 206 and the seconddielectric layer 212 are buried between the first semiconductorsubstrate 202 and the epitaxial Ge layer 204. The bonding condition andchamber are similar to the one used for form the GOI substrate 100previously described. The first semiconductor substrate 202, theepitaxial Ge layer 204, the first dielectric layer 206, the seconddielectric layer 212, and the second semiconductor substrate 210 form abonded wafer pair after the bonding.

After the bonding, the first semiconductor substrate 202 is removed andthe remaining structure forms the GOI substrate 200. In one embodiment,prior to the removal of the first semiconductor substrate 202, thebonded wafer pair is annealed using conventional methods or methodspreviously described to strengthen the bonding interface. In oneembodiment, the first semiconductor substrate 202 is removed by grindingback (e.g., using CMP) to expose the epitaxial Ge layer 204.Alternatively, the first semiconductor substrate 202 is removed by anetching process to expose the epitaxial Ge layer 204. Alternatively yet,the first semiconductor substrate 202 can be removed by a combination ofa grind back and an etching processes. The first semiconductor substrate202 can also be removed similarly to the removal of the firstsemiconductor substrate 102 previously described. After the firstsemiconductor substrate 202 is removed, the GOI 200 is formed having theepitaxial Ge layer 204, the first and second dielectric layers 206 and212 bonded to the second semiconductor substrate 210.

FIGS. 3A-3F illustrate various stages of forming a GOI substrate 300 inaccordance to some embodiments of the present invention. The GOIsubstrate 300 is similar to the GOI substrate 100 and 200 except thatthe first semiconductor substrate includes a cleaving plane 311 forfacilitate the removal of the first semiconductor substrate after thebonding. In addition, the second semiconductor substrate may optionallybut need not include a second dielectric layer 312.

In FIG. 3A, a first semiconductor substrate 302 is provided. The firstsemiconductor substrate 302 can be any suitable material that anepitaxial Ge layer can be formed thereon and be removed from. Thesemiconductor substrate 302 is typically a Si wafer.

In FIG. 3B, an epitaxial Ge layer 304 is formed on top of the firstsemiconductor substrate 302. In one embodiment, the epitaxial Ge layer304 has a surface with a roughness approximately greater than 2 nm RMS.In another embodiment, the epitaxial Ge layer 304 has a surface with aroughness approximately greater than 4 nm RMS. The epitaxial Ge layer304 has a thickness 301 that may be less than 3000 Å. In someembodiment, the epitaxial Ge layer 304 has a thickness 301 ranging fromabout 100-4000 Å. The epitaxial Ge layer 304 can be formed usingconventional methods such as chemical vapor deposition (CVD) or plasmaenhanced CVP as is known in the art.

In FIG. 3C, a first dielectric layer 306 is formed over the epitaxial Gelayer 304. As shown in FIG. 3B, the surface of the epitaxial Ge layer304 is rough and thus difficult for a direct wafer bonding to theepitaxial Ge layer 304. Forming the first dielectric layer 306 over theepitaxial Ge layer 304 covers the rough surface on the epitaxial Gelayer 304 and allows bonding to the first dielectric layer 306. In thisway, the epitaxial Ge layer 304 can be bonded to another wafer throughthe first dielectric layer 306. The first dielectric layer 306 issimilar to the dielectric layer 106 previously described and can be anoxide film such as SiO₃, Si₃N₄, HfO₃, SrTiO₃, Ta₃O₅, TiO₃, ZrO₃, Al₃O₃,and Y₃O₃, etc. The first dielectric layer 306 is formed by aconventional method such as CVD or plasma enhanced CVD.

In one embodiment, the first dielectric layer 306 is sufficiently thickto cover the roughness on the surface of the epitaxial Ge layer 304. Inone embodiment, the first dielectric layer 306 has a thickness 303greater than 3000 Å. In another embodiment, the first dielectric layer306 has a thickness 303 greater than 6000 Å.

In FIG. 3C, ion implantation 320 is used to bombard ions (e.g., hydrogenion) into the first semiconductor substrate 302. The ion implantation320 creates a cleaving plane 311 that later facilitates the removal ofthe first semiconductor substrate 302 after bonding. The cleaving plane311 can be created at a location that is convenient for the removal ofthe first semiconductor substrate 302 after the bonding. In oneembodiment, the ion implantation 320 bombards ions into the firstsemiconductor substrate 302 at a location near the interface 313 betweenthe epitaxial Ge layer 204 and the first semiconductor substrate 302.The ion implantation 320 may be deeper into the first semiconductorsubstrate 302 if desired. In one embodiment, a conventional ionimplantation process is used to implant energetic particles or ions(e.g., hydrogen particles, H₂ ⁺or H⁺) through the top surface of thefirst dielectric layer 306 to a predetermined depth in the firstsemiconductor substrate 302. The cleaving plane is parallel orsubstantially parallel to the surface of the first dielectric layer 306.In one embodiment, the ions are implanted to a dosage of about 5×10¹⁶ to5×10¹⁸, or 1×10¹⁷. A smoothing process can be used after the firstsemiconductor substrate 302 is cleaved off to smooth out the surface forthe epitaxial Ge layer 304.

In one embodiment, portions of the first dielectric layer 306 areremoved (e.g., by polishing or etching) to provide the first dielectriclayer 306 with a smooth, substantially particle free., and clean surface(to repair any damages caused by the ion implantation). A smooth surfacewill facilitate the bonding of the first dielectric layer 306 to anothersurface. In addition, the first dielectric layer 306 may be thinned to adesired thickness in the removal process. For some embodiments, thefirst dielectric layer 306 may be thinned from the thickness 303 to athickness 307 shown in FIG. 3F that is smaller than the thickness 303.In one embodiment, the thickness 303 is about 3000 Å and the thickness307 is about 500-2000 Å. In one embodiment, the first dielectric layer306 is polished using a conventional method such as chemical mechanicalpolishing (CMP) to remove some of the first dielectric layer 306.

In FIG. 3D, a second semiconductor substrate 310 is provided. The secondsemiconductor substrate 310 can be any suitable substrate typically usedfor fabricating an electronic device therein. The second semiconductorsubstrate 310 can be a Si wafer.

In FIG. 3E, a second dielectric layer 312 is formed on top of the secondsemiconductor substrate 310. The second dielectric layer 312 is similarto the first dielectric layer 306 and can be formed of similar materialand using similar methods as those used for the first dielectric layer306. The second dielectric layer 312 has a predetermined thickness 305.The second dielectric layer 312 and the first dielectric layer 306should have a combined thickness 309 that is sufficient to insulate thedevice that will be formed on the GOI substrate 300. In one embodiment,the combined thickness 309 is between 500-3500 Å.

In FIG. 3F, the first semiconductor substrate 302 and the secondsemiconductor substrate 310 are bonded together. In particular, thefirst dielectric layer 306 is bonded to the second dielectric layer 312.After the bonding, the first dielectric layer 306 and the seconddielectric layer 312 are buried between the first semiconductorsubstrate 302 and the epitaxial Ge layer 304. The bonding condition andchamber are similar to the one used for form the GOI substrate 100previously described. The first semiconductor substrate 302, theepitaxial Ge layer 304, the first dielectric layer 304, the seconddielectric layer 312, and the second semiconductor substrate 310 form abonded wafer pair after the bonding. After the bonding, the firstsemiconductor substrate 302 is removed and the remaining structure isthe GOI substrate 300.

In one embodiment, prior to the removal of the first semiconductorsubstrate 302, the bonded wafer pair is annealed using conventionalmethods or methods previously described to strengthen the bondinginterface. In one embodiment, the first semiconductor substrate 302 isremoved a nitrogen jet to initiate the cleaving of the firstsemiconductor substrate 302 at the cleaving plane 311. Alternatively,the first semiconductor substrate 302 is removed by an annealing processto thermally cleave the first semiconductor substrate 302 at thecleaving plane 311. The annealing process used to thermally cleave thefirst semiconductor substrate 302 can be similar to the annealingprocess used to strengthen the bonding of the bonded wafer pair. Theannealing process used to thermally cleave the first semiconductorsubstrate 302 typically occurs at a temperature that is sufficient toinitiate the cleaving of the first semiconductor substrate 302. Thecleaving temperature ranges from 100° C. to 600° C. In one embodiment,the cleaving temperature is approximately 150° C. for ion implantationthat creates a cleaving plane within the epitaxial Ge layer 304. Inanother embodiment, the cleaving temperature is approximately 450° C.for ion implantation that creates a cleaving plane within the firstsemiconductor substrate 302.

The removal of the first semiconductor substrate 302 exposes theepitaxial Ge layer 304. After the first semiconductor substrate 302 isremoved, the GOI 300 is formed having the epitaxial Ge layer 304, thefirst and second dielectric layers 306 and 312 bonded to the secondsemiconductor substrate 310.

In one embodiment, after cleaving, the epitaxial Ge layer 304 may have arough surface on the side where the first semiconductor substrate 302was removed. The epitaxial Ge layer 304 may be polished (and if needed,further thinned) using a chemical mechanical polishing (CMP), a wetchemical treatment, or wet/dry etching method well known in the art. Inone embodiment, a conventional CMP tool is used to polish and/or torepair any surface damage and/or roughness in the epitaxial Ge layer304.

FIG. 4 illustrates an exemplary embodiment of a method 400 of forming aGOI substrate (e.g., the GOI substrate 100). At operation 402, anepitaxial Ge layer is formed on top of a first semiconductor substrate,which may be a Si wafer. At operation 404, a first dielectric film(e.g., an oxide or a nitride film) is formed on top of the epitaxial Gelayer. At operation 606, a second semiconductor substrate is provided.The second semiconductor substrate may have a second dielectric filmformed on top of the second semiconductor substrate. At operation 608,the first semiconductor substrate is bonded to the second semiconductorsubstrate in such a way that the first dielectric film is bonded to thesecond semiconductor substrate or alternatively, the first dielectricfilm is bonded to the second dielectric film. At operation 610, thefirst semiconductor substrate is removed to expose the epitaxial Gelayer, e.g., by using a grind back and/or an etching process.

FIG. 5 illustrates another exemplary method 500 of forming a GOIsubstrate (e.g., the GOI substrate 300). At operation 502, an epitaxialGe layer is formed on top of a first semiconductor substrate, which maybe a Si wafer. At operation 504, a first dielectric film (e.g., an oxideor a nitride film) is formed on top of the epitaxial Ge layer. Atoperation 506, ion implantation is used to implant particles into thefirst semiconductor substrate. In one embodiment, the ions are implantedinto the first semiconductor substrate using hydrogen implantation. Theion implantation creates a cleaving plane within the first semiconductorsubstrate.

At operation 508, a second semiconductor substrate is provided. Thesecond semiconductor substrate may have a second dielectric film formedon top of the second semiconductor substrate. At operation 510, thefirst semiconductor substrate is bonded to the second semiconductorsubstrate in such a way that the first dielectric film is bonded to thesecond semiconductor substrate or alternatively, the first dielectricfilm is bonded to the second dielectric film. At operation 512, thefirst semiconductor substrate is removed to expose the epitaxial Gelayer, e.g., by using a thermal cleaving process or jetting process.

FIG. 6 illustrates another exemplary method 600 of forming a GOIsubstrate (e.g., the GOI substrate 300). At operation 602, an epitaxialGe layer is formed on top of a first semiconductor substrate, which maybe a Si wafer. At operation 604, a first dielectric film (e.g., an oxideor a nitride film) is formed on top of the epitaxial Ge layer. Atoperation 606, ion implantation is used to implant particles into thefirst semiconductor substrate. In one embodiment, the ions are implantedinto the first semiconductor substrate using hydrogen implantation. Theion implantation creates a cleaving plane within the first semiconductorsubstrate. In addition, the first dielectric layer is polished (e.g.,using CMP or etching) to provide a smooth and/or flat surface forbonding. The polishing process occurs after the ion implantation torepair any damages to the surface of the first dielectric layer.

At operation 608, a second semiconductor substrate is provided. Thesecond semiconductor substrate may have a second dielectric film formedon top of the second semiconductor substrate. At operation 610, thefirst semiconductor substrate is bonded to the second semiconductorsubstrate in such a way that the first dielectric film is bonded to thesecond semiconductor substrate or alternatively, the first dielectricfilm is bonded to the second dielectric film. At operation 612, thefirst semiconductor substrate is removed to expose the epitaxial Gelayer, e.g., by using a thermal cleaving process or jetting process.

FIG. 7 illustrates an exemplary GOI substrate 700 formed in accordanceto some of the embodiments of the present invention. The GOI substrate700 can be the GOI substrate 100, 200, 300, or 400 previously described.The GOI substrate 700 includes a semiconductor substrate 710, which isbonded to a dielectric layer 712 and a dielectric 706. The dielectriclayer 706 is formed over an epitaxial Ge layer 704 as previouslydescribed. In certain embodiments, the dielectric layer 712 iseliminated and only the dielectric layer 706 is present and bonded tothe semiconductor substrate 710 as previously described.

FIG. 8 illustrates an exemplary semiconductor device 701 fabricated inthe GOI substrate 700. In one embodiment, the semiconductor device 701is a transistor. The semiconductor device 701 includes the GOI substrate700, isolation trenches 720, source drain regions 748, a gate dielectric742, a gate electrode 744, spacers 746, and optionally, source/draincontacts 700.

In one embodiment, the epitaxial Ge layer 704 of the GOI substrate 700may be moderately doped (e.g., 1×10¹⁶ per cm³ to 1×10¹⁵ per cm³). Thedoping concentration is chosen to properly target the transistorthreshold voltage. Isolation trenches 720 may be formed into the Gelayer 704 using conventional methods (e.g., etching). The gatedielectric 742, gate electrode 744, and spacers 746 can be formed on thetop surface of the Ge layer 704 using conventional methods (e.g., filmdeposition and patterning). In one embodiment, the gate dielectric 742is made out of a high-k dielectric material. The gate electrode 744 canbe made out of a metal containing material, such as titanium nitride ortungsten, for a metal gate. The gate electrode 744 can also be dopedpolysilicon. The spacers 746, typically comprise of a combination ofSiO₂ and Si₃N₄. The source and drain regions 748 are formed in the Gelayer 704 using conventional methods. The source and drain regions 748may be heavily doped with a dopant concentration of 1×10²⁰ per cm³.

Source/drain contacts 740 can be made of nickel-germanium (NiGe) andformed on the Ge layer 704 over the regions that are not covered by thegate dielectric 742 and the spacers 746. In one embodiment, the NiGe isformed by a low-temperature annealing method using an annealingtemperature of about 400° C. to 600° C. Depositing a metal (e.g.,nickel) that reacts with the material in the transistor body cansubstantially lower the resistivity of the source and drain contacts.Conventional contacts can also be formed instead to establish contactsto the source/drain regions 748.

Those skilled in the art will recognize that the features mentioned inFIG. 5 and other features may be used or may be left out, depending uponthe particular function of the device 701. For some embodiments, afterthe formation of the NiGe, the device 701 is subjected to conventionprocess of forming interlayer dielectric deposition, contact patterning,metalization, etc.

FIG. 9 illustrates another exemplary semiconductor device 702 that canbe fabricated in the GOI substrate 700. The exemplary semiconductordevice 702 is an integrated detector that may provide electrical outputdriven by an optical input to integrated circuits in a substrate. Thedevice 702 includes the GOI substrate 700 having the epitaxial Ge layer704. Isolation trenches 720 are formed into the epitaxial Ge layer 704using conventional methods. The device 702 further includes a waveguide752 formed on top of the epitaxial Ge layer 704 using conventionalmethods. The waveguide 752 is further encapsulated by a dielectric layer750. It is common for the integrated structure to have the waveguide 752be made out of a relatively high-refractive index material (e.g., Si₃N₄which has a refractive index n=2.05). The waveguide 752 is typicallyencapsulated in a material with lower refractive index (e.g., SiO₂ whichhas a refractive index n=1.46). When light is introduced in thewaveguide 752 having the high refractive index material, the light willbe confined there. The waveguide 752 then “guides” the light from thesource (typically an external laser) to the detector (in this case, theGe layer 704).

Detector electrodes 754 are formed in vias created in the dielectriclayer 750. In order for the Ge layer 704 to function as a detector, abias must be applied across it. Any light shining on the detector thengenerates electron-hole pairs. These pairs are swept by the bias field,causing current to flow through the Ge layer 704. There is an electricalresponse to a light impulse. The detector electrodes 754 are needed toprovide the required bias. In one embodiment, a conductive material,such as metal, is deposited and then patterned using conventionalmethods. In this embodiment, the detector electrodes 754 are depositedby a damascene process, well practiced in the field.

While the invention has been described in terms of several embodiments,those of ordinary skill in the art will recognize that the invention isnot limited to the embodiments described. The method and apparatus ofthe invention, but can be practiced with modification and alterationwithin the spirit and scope of the appended claims. The description isthus to be regarded as illustrative instead of limiting.

Having disclosed exemplary embodiments, modifications and variations maybe made to the disclosed embodiments while remaining within the spiritand scope of the invention as defined by the appended claims.

1. A method of forming a germanium-on-insulator (GOI) substratecomprising: forming an epitaxial germanium layer on top of a firstsubstrate; forming a first dielectric film on top of the epitaxialgermanium layer; providing a second substrate; bonding the firstsubstrate to the second substrate by bonding the first dielectric filmto the second substrate, the bonding resulted in a bonded wafer pair;and removing the first substrate after the bonding to expose epitaxialgermanium layer to form the GOI substrate.
 2. A method as in claim 1further comprises forming a second dielectric film on top of the secondsubstrate wherein the bonding of the first substrate to the secondsubstrate further comprises bonding the first dielectric film to thesecond dielectric film.
 3. A method as in claim 1 wherein the removingof the first substrate after the bonding includes one of a grind backprocess, an etching process, and an ion exfoliation process.
 4. A methodas in claim 1 further comprising: polishing the surface of the firstdielectric film prior to the bonding.
 5. A method as in claim 1 furthercomprises causing an ion implantation to the first substrate through thefirst dielectric film to define a cleaving plane.
 6. A method as inclaim 5 further comprises forming a second dielectric film on top of thesecond substrate wherein the bonding of the first substrate to thesecond substrate further comprises bonding the first dielectric film tothe second dielectric film.
 7. A method as in claim 7 wherein theremoving of the first substrate after the bonding includes cleaving offthe first substrate.
 8. A method as in claim 5 further comprising:polishing the surface of the first dielectric film after the ionimplantation, the polishing performs at least one of providing a smoothsurface for the first dielectric film, repairing surface damages on thefirst dielectric film, and providing a clean surface for bonding.
 9. Amethod as in claim 1 wherein each of the first substrate and the secondsubstrate semiconductor wafer is selected from a group consisting of asilicon (Si) substrate, a monocrystalline Si substrate, apolycrystalline Si substrate, a Si-containing substrate, a Si substratehaving an oxide layer, a silicon-on-insulator (SOI) substrate, a galliumarsenide substrate, and Ge-containing substrate.
 10. A method as inclaim 1 further comprising causing a surface activation to the topsurface of the first dielectric film and at least one surface of thesecond substrate to facilitate the bonding.
 11. A method as in claim 1further comprises annealing the bonded wafer pair at a predeterminedannealing temperature, wherein the annealing temperature is achievedwith a temperature ramp rate of approximately 1° C./minute.
 12. A methodof bonding a germanium layer having a rough surface to a substratecomprising: forming an epitaxial germanium layer on top of a firstsubstrate, the epitaxial germanium layer having a rough surface, therough surface has a roughness value approximately greater than 2 nm RMS;forming a first dielectric film on top of the rough surface; bonding thefirst dielectric film to a second substrate, the bonding resulted in abonded wafer pair wherein the first dielectric film is located betweenthe epitaxial germanium layer and the second substrate; and removing thefirst substrate after the bonding to expose epitaxial germanium layer.13. A method as in claim 12 further comprises forming a seconddielectric film on top of the second substrate wherein the bonding ofthe first dielectric film to the second substrate includes bonding thefirst dielectric film to the second dielectric film.
 14. A method as inclaim 12 wherein the removing of the first substrate after the bondingincludes one of a grind back process, an etching process, and an ionexfoliation process.
 15. A method as in claim 12 further comprising:polishing the surface of the first dielectric film prior to the bonding.16. A method as in claim 12 further comprises causing an ionimplantation to the first substrate through the first dielectric film todefine a cleaving plane.
 17. A method as in claim 16 wherein theremoving of the first substrate after the bonding includes cleaving offthe first substrate.
 18. A method as in claim 17 further comprising:polishing the surface of the first dielectric film after the ionimplantation, the polishing performs at least one of providing a smoothsurface for the first dielectric film, repairing surface damages on thefirst dielectric film, and providing a clean surface for bonding.
 19. Amethod as in claim 12 wherein each of the first substrate and the secondsubstrate semiconductor wafer is selected from a group consisting of asilicon (Si) substrate, a monocrystalline Si substrate, apolycrystalline Si substrate, a Si-containing substrate, a Si substratehaving an oxide layer, a silicon-on-insulator (SOI) substrate, a galliumarsenide substrate, and Ge-containing substrate.
 20. A method as inclaim 12 further comprising causing a surface activation to the topsurface of the first dielectric film and at least one surface of thesecond substrate to facilitate the bonding.
 21. A method as in claim 12further comprises annealing the bonded wafer pair at a predeterminedannealing temperature, wherein the annealing temperature is achievedwith a temperature ramp rate of approximately 1° C./minute.
 22. A methodof fabricating a semiconductor device comprising: forming an epitaxialgermanium layer on top of a first substrate; forming a first dielectricfilm on top of the epitaxial germanium layer; providing a secondsubstrate; bonding the first substrate to the second substrate bybonding the first dielectric film to the second substrate, the bondingresulted in a bonded wafer pair; removing the first substrate after thebonding to expose epitaxial germanium layer to form a GOI substrate; andforming an electronic device on the GOI substrate.
 23. A method as inclaim 22 wherein the electronic device includes one of a transistor anda detector.
 24. A method as in claim 23 wherein the transistor includesa gate dielectric, a gate electrode, spacers and source/drain regions.25. A method as in claim 23 wherein the detector includes a waveguideencapsulated by an oxide layer and at least one electrode.
 26. A methodas in claim 22 further comprises forming a second dielectric film on topof the second substrate wherein the bonding of the first substrate tothe second substrate further comprises bonding the first dielectric filmto the second dielectric film.
 27. A method as in claim 22 wherein theremoving of the first substrate after the bonding includes one of agrind back process, an etching process, and an ion exfoliation process.28. A method as in claim 22 further comprising: polishing the surface ofthe first dielectric film prior to the bonding.
 29. A method as in claim22 further comprises causing an ion implantation to the first substratethrough the first dielectric film to define a cleaving plane.
 30. Amethod as in claim 22 wherein the removing of the first substrate afterthe bonding includes cleaving off the first substrate.
 31. Asemiconductor assembly comprising: an epitaxial germanium layer formedon top of a first substrate, the epitaxial germanium layer having arough surface; a first dielectric film is formed on top of the epitaxialgermanium layer over the rough surface; a second substrate bonding tothe first substrate with the first dielectric film bonding to the secondsubstrate, the bonding resulted in a bonded wafer pair; and wherein thefirst substrate is removeable after the bonding to expose epitaxialgermanium layer to form a GOI substrate.
 32. A semiconductor assembly asin claim 31 wherein the rough surface has a roughness valueapproximately greater than 2 nm RMS.